Welcome to STG-Rust's documentation!
======================================

STG (Structured Testbench Generation) is a high-performance Rust tool that automatically generates comprehensive testbenches for Verilog/SystemVerilog designs.

.. toctree::
   :maxdepth: 2
   :caption: Getting Started

   getting_started

.. toctree::
   :maxdepth: 2
   :caption: User Guide

   user_guide/modes_overview
   user_guide/sv_mode
   user_guide/cc_sc_mode
   user_guide/multi_dut
   user_guide/fsm_coverage
   user_guide/advanced

.. toctree::
   :maxdepth: 2
   :caption: Reference

   reference/cli

.. toctree::
   :maxdepth: 2
   :caption: Additional Resources

   examples
   troubleshooting


Indices and tables
==================

* :ref:`genindex`
* :ref:`modindex`
* :ref:`search`