C++ / SystemC Mode

C++/SystemC mode provides a two-stage workflow where you implement a golden model in C++ (or SystemC), giving you maximum flexibility for reference implementations.

CC Mode (C++ Testbench)

Use --cc for C++ testbenches. The golden model uses standard C++ integer types.

Stage 1: Generate Golden Model Template

stg generate \
  --verilog path/to/dut.v \
  --module dut_module_name \
  --type <design_type> \
  --out testbench.cpp \
  --out-header golden_model.h \
  --cc \
  [additional options...]

This generates:

golden_model.h — A C++ header template with signal declarations
testbench.cpp — The C++ testbench that includes the golden model

Generated golden model structure:

#ifndef GOLDEN_MODEL_H
#define GOLDEN_MODEL_H

#include <cstdint>

class GoldenModel {
public:
    // Input signals
    uint8_t a;
    uint8_t b;
    uint8_t op;

    // Output signals
    uint8_t out;

    // Implement your golden model logic here
    void eval() {
        // TODO: Implement combinational logic
    }

    // For sequential designs
    void posedge_clk() {
        // TODO: Implement sequential logic
    }
};

#endif

Stage 2: Implement the Golden Model

Edit golden_model.h to implement your logic. Example for an ALU:

void eval() {
    switch (op) {
        case 0: out = a + b; break;
        case 1: out = a - b; break;
        case 2: out = a & b; break;
        case 3: out = a | b; break;
        case 4: out = a ^ b; break;
        case 5: out = a << b; break;
        case 6: out = a >> b; break;
        case 7: out = (int8_t)a >> b; break;
    }
}

Stage 3: Compile with Implemented Golden Model

stg generate \
  --verilog path/to/dut.v \
  --module dut_module_name \
  --golden golden_model.h \
  --type <design_type> \
  --out testbench.cpp \
  --out-exe testbench_exe \
  --cc \
  [additional options...]

./testbench_exe

SC Mode (SystemC Testbench)

Use --sc for SystemC-style golden models with sc_uint<N> data types.

Stage 1: Generate SystemC Golden Model Template

stg generate \
  --verilog path/to/dut.v \
  --module dut_module_name \
  --type <design_type> \
  --out testbench.cpp \
  --out-header golden_model_sc.h \
  --sc \
  [additional options...]

Generated SystemC golden model:

#ifndef GOLDEN_MODEL_SC_H
#define GOLDEN_MODEL_SC_H

#include <systemc>

class GoldenModel {
public:
    sc_dt::sc_uint<4> a;
    sc_dt::sc_uint<4> b;
    sc_dt::sc_uint<3> op;
    sc_dt::sc_uint<4> out;

    void eval() {
        // TODO: Implement combinational logic using sc_uint
    }
};

#endif

Stage 2: Implement with SystemC Types

void posedge_clk() {
    if (rst_n == 0) {
        out = 0;
        return;
    }

    if (en) {
        uint32_t val = out.to_uint();
        out = (val + 1) & 0xF;
    }
}

Stage 3: Compile with SystemC Golden Model

stg generate \
  --verilog path/to/dut.v \
  --module dut_module_name \
  --golden golden_model_sc.h \
  --type <design_type> \
  --out testbench.cpp \
  --out-exe testbench_exe \
  --sc \
  [additional options...]

./testbench_exe

Recompiling a Modified C++/SystemC Testbench

If you modify the generated C++ testbench, use stg compile:

stg compile \
  --verilog path/to/dut.v \
  --module dut_module_name \
  --golden golden_model.h \
  --testbench testbench.cpp \
  --out-exe testbench_exe \
  --cc   # or --sc for SystemC