SystemVerilog Mode

In SystemVerilog (SV) mode, both your DUT and golden reference are Verilog/SystemVerilog modules. This is the simplest workflow and is the default mode.

Basic Workflow

Verilog files can be specified as positional arguments or with the --verilog flag — both are equivalent:

# Positional arguments
stg generate path/to/dut.v --golden path/to/golden.v --type <design_type> --out tb.sv

# Explicit --verilog flag
stg generate --verilog path/to/dut.v --golden path/to/golden.v --type <design_type> --out tb.sv

Generate Testbench Only

Generate a testbench file without compiling:

stg generate \
  --verilog path/to/dut.v \
  --module dut_module_name \
  --golden path/to/golden.v \
  --golden-module golden_module_name \
  --type <design_type> \
  --out testbench.sv

Generate and Compile

With iverilog

stg generate \
  --verilog path/to/dut.v \
  --module dut_module_name \
  --golden path/to/golden.v \
  --golden-module golden_module_name \
  --type <design_type> \
  --out testbench.sv \
  --out-exe testbench_exe

./testbench_exe

With Verilator

stg generate \
  --verilog path/to/dut.v \
  --module dut_module_name \
  --golden path/to/golden.v \
  --golden-module golden_module_name \
  --type <design_type> \
  --out testbench.sv \
  --out-exe testbench_exe \
  --verilator

./testbench_exe

With Verilator MPI (Parallel Execution)

For large designs, MPI enables parallel test execution:

stg generate \
  --verilog path/to/dut.v \
  --module dut_module_name \
  --golden path/to/golden.v \
  --golden-module golden_module_name \
  --type <design_type> \
  --out testbench.sv \
  --out-exe testbench_exe \
  --verilator-mpi

mpirun -np 4 ./testbench_exe

Recompiling a Modified Testbench

If you manually edit the generated testbench, use stg compile to recompile:

# With iverilog
stg compile \
  --verilog path/to/dut.v \
  --golden path/to/golden.v \
  --testbench testbench.sv \
  --out-exe testbench_exe

# With Verilator
stg compile \
  --verilog path/to/dut.v \
  --golden path/to/golden.v \
  --testbench testbench.sv \
  --out-exe testbench_exe \
  --verilator

Module Emplacement

When DUT and golden modules share the same name, use --emplace-module to embed both into the testbench file with automatic prefix renaming:

stg generate \
  --verilog dut.v \
  --golden golden.v \
  --type combinational \
  --out tb.sv \
  --emplace-module

This creates a single .sv file where module names are prefixed with dut_ or golden_ to avoid conflicts.

Note

Module emplacement is only available in SV mode. In CC/SC mode, Verilator handles renaming automatically.