Modes and Design Types

This page explains the testbench generation modes and the supported design types in STG.

Testbench Modes

STG supports two main approaches to testbench generation: SystemVerilog (SV) mode and C++/SystemC (CC/SC) mode.

Mode

Testbench Language

Golden Model

Compiler

Use Case

SV (default)

SystemVerilog

Verilog/SystemVerilog

iverilog or Verilator

Standard workflow, easy setup

CC

C++

C++ header

Verilator

Custom golden model, high performance

SC

C++ with SystemC

SystemC header

Verilator

SystemC ecosystem, sc_uint types

SystemVerilog Mode (SV)

  • Both DUT and golden reference are Verilog/SystemVerilog modules

  • Uses iverilog or Verilator for compilation

  • Single-stage workflow: provide DUT, golden, and generate

  • Best for: simple designs, standard verification workflow

See the SystemVerilog Mode Guide for full details.

C++ Mode (CC)

  • DUT is Verilog, golden model is a C++ header file

  • Uses Verilator exclusively for DUT compilation

  • Two-stage workflow:

    1. Generate a golden model header template with --out-header

    2. Implement the golden model, then compile with --golden

  • Best for: complex golden models, custom C++ logic, maximum performance

SystemC Mode (SC)

  • Similar to CC mode but uses SystemC types (sc_uint<N>)

  • Two-stage workflow like CC mode

  • Best for: SystemC ecosystem integration, bit-accurate types

See the C++/SystemC Mode Guide for full details on both CC and SC modes.

Design Types

STG supports three fundamental design types, specified with --type:

combinational

Pure combinational logic with no clock or state elements.

  • Test approach: Exhaustively enumerate control signals, randomly sample data signals

  • Examples: ALUs, multiplexers, decoders, encoders

  • Golden model function: eval()

stg generate --verilog dut.v --golden golden.v --type combinational --out tb.sv

seq_clocked

Clocked sequential design with continuous operation.

  • Requires: clock signal (and usually a reset signal)

  • Test approach: Apply random control/data patterns over multiple clock cycles

  • Examples: Counters, shift registers, timers, pipelines

  • Golden model function: posedge_clk()

stg generate --verilog dut.v --golden golden.v --type seq_clocked --out tb.sv \
  --clock clk --reset rst_n --reset-active low

seq_done

Sequential design with transaction-based operation that signals completion.

  • Requires: clock, reset, and a done/valid signal

  • Test approach: Start a transaction, wait for the done signal, then check results

  • Examples: GCD calculators, dividers, multi-cycle state machines

  • Golden model function: posedge_clk() (with completion tracking)

stg generate --verilog dut.v --golden golden.v --type seq_done --out tb.sv \
  --clock clk --reset rst --reset-active high --done done

Signal Classification

STG automatically classifies input signals into two categories:

Category

Behavior

Typical Signals

Control signals

Exhaustively enumerated (up to 2^26 combinations)

op, mode, cmd, sel (narrow, 1–4 bits)

Data signals

Randomly sampled (default: 1024 per control vector)

a, b, data, addr (wider, 8+ bits)

You can override automatic classification with --control-signals and --data-signals. Use stg identify to preview what STG detects:

stg identify --verilog dut.v --module my_module --type combinational --out signals.yaml

Choosing the Right Mode

Scenario

Recommended Mode

Quick verification with Verilog golden

SV mode

Complex golden model logic

CC mode

Need SystemC types for bit accuracy

SC mode

Large design, need speed

CC/SC mode with Verilator

Multiple DUT comparison

CC/SC mode (automatic prefix handling)

FSM state coverage

generate-fsm command (see FSM Coverage)