Welcome to STG-Rust’s documentation!

STG (Structured Testbench Generation) is a high-performance Rust tool that automatically generates comprehensive testbenches for Verilog/SystemVerilog designs.

Getting Started

• Getting Started
  • What is STG?
  • Prerequisites
  • Installation
  • Quick Start
  • Available Commands
  • What’s Next?

User Guide

• Modes and Design Types
  • Testbench Modes
  • Design Types
  • Signal Classification
  • Choosing the Right Mode
• SystemVerilog Mode
  • Basic Workflow
  • Generate Testbench Only
  • Generate and Compile
  • Recompiling a Modified Testbench
  • Module Emplacement
  • See Also
• C++ / SystemC Mode
  • CC Mode (C++ Testbench)
  • SC Mode (SystemC Testbench)
  • Recompiling a Modified C++/SystemC Testbench
  • See Also
• Multi-DUT Support
  • Basic Multi-DUT Usage
  • Module Selection
  • Multi-DUT in SystemVerilog Mode
  • Multi-DUT in C++/SystemC Mode
  • Multi-DUT with Sequential Designs
  • Test Statistics (JSON Output)
  • See Also
• FSM-Based Coverage
  • When to Use It
  • Quick Start
  • FSM Extraction Methods
  • State Analysis Caching
  • Examples
  • Output
  • Transition Verification Model
  • Optional Line Execution Check
  • Edge Status in Statistics
  • Verilator Binary Selection
  • Troubleshooting
  • See Also
• Advanced Features
  • YAML Configuration
  • Verilator Coverage Analysis
  • Custom Compiler Flags
  • Tips and Best Practices
  • See Also

Reference

• CLI Reference
  • Global Options
  • stg generate
  • stg generate-fsm
  • stg identify
  • stg parse
  • stg compile
  • Runtime Arguments

Additional Resources

• Examples
  • Combinational Logic — ALU
  • Sequential Clocked — Counter
  • Sequential with Done Signal — GCD
  • Multi-DUT Comparison — ALU Implementations
  • FSM Coverage — Traffic Light
  • FSM Coverage — Sequence Detector
  • See Also
• Troubleshooting
  • Verilog Parsing Issues
  • C++/SystemC Mode Issues
  • Compilation Issues
  • Signal Classification Issues
  • FSM Coverage Issues
  • Runtime Issues
  • Getting Help

Indices and tables

• Index

• Module Index

• Search Page